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SX1211
WIRELESS & SENSING
5.5.9. Packet Mode Example
Configure all data processing related registers listed below appropriately. In this example we assume CRC is
enabled with autoclear on.
Table 25: Relevant Configuration Registers in Packet Mode (data processing related only)
Tx
Rx
Description
Data_mode_x
X
X
Defines data operation mode ( Packet)
fixed format only
MCParam
IRQParam
RXParam
SYNCParam
PKTParam
(1)
Fifo_size
Fifo_thresh
Rx_stby_irq_0
Rx_stby_irq_1
Tx_irq_1
Tx_start_irq_0
Sync_size
Sync_tol
Sync_value
Manchester_on
Payload_length
Node_adrs
Pkt_format
Preamble_size
Whitening_on
CRC_on
Adrs_filt
CRC_autoclr
Fifo_stby_access
X
X
X
X
X
X
X
X (1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Defines FIFO size
Defines FIFO threshold
Defines IRQ_0 source in Rx & Stby modes
Defines IRQ_1 source in Rx & Stby modes
Defines IRQ_1 source in Tx mode
Defines Tx start condition and IRQ_0 source
Defines Sync word size
Defines the error tolerance on Sync word detection
Defines Sync word value
Enables Manchester encoding/decoding
Length in fixed format, max Rx length in variable format
Defines node address for Rx address filtering
Defines packet format (fixed or variable length)
Defines the size of preamble to be transmitted
Enables whitening/de-whitening process
Enables CRC calculation/check
Enables and defines address filtering
Enables FIFO autoclear if CRC failed
Defines FIFO access in Stby mode
Tx Mode :
Program Tx start condition and IRQs: Start Tx when FIFO not empty (Tx_start_irq_0=1) and IRQ_1 mapped to
Tx_done (Tx_irq_1=1)
Go to Stby mode
Write all payload bytes into FIFO (Fifo_stby_access=0, Stby interrupts can be used if needed)
Go to Tx mode. When Tx is ready (automatically handled) Tx starts (Tx_start_irq_0=1).
Wait for Tx_done interrupt (+1 bit period)
Go to Sleep mode
Rx Mode :
Program Rx/Stby interrupts: IRQ_0 mapped to /Fifoempty (Rx_stby_irq_0=10) and IRQ_1 mapped to CRC_OK
(Rx_stby_irq_1=00)
Go to Rx (note that Rx is not ready immediately, see section 7.3.1
Wait for CRC_OK interrupt
Go to Stby
Read payload bytes from FIFO until /Fifoempty goes low. (Fifo_stby_access =1)
Go to Sleep mode
5.5.10. Additional Information
If the number of bytes filled for transmission is greater than the actual length of the packet to be transmitted and
Tx_start_irq_0 = 1, then the FIFO is cleared after the packet has been transmitted. Thus the extra bytes in the
Rev 8 – February 2013
Page 56 of 92
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